1. Technical Field
The present invention relates to semiconductor chip design, and more particularly to a design tool for optimizing and providing ground rules waivers for chip designs and fabrication procedures.
2. Description of the Related Art
Calculating 2-dimensional and intra-level intersect areas for structures in a semiconductor design remains a challenge within the semiconductor industry. Intersect areas refer to areas common to a pair of layers in layouts of devices or components on a semiconductor chip. These areas are constrained by ground rules which provide requirements for spacings between the components, the component sizes, etc.
Ground rules are restrictions with regard to the geometry of the layout that must be adhered to by the designer of a Very Large Scale Circuit (VLSI) chip. Examples of ground rules are minimum width of a channel, minimum distance between two corners, minimum distance between two features and the like, as is known in the art. Such considerations include component placement on multiple levels of the chip design and therefore in turn the ground rules determine intra-level intersect areas which are then subject to their own rules.
In earlier technology generations, it was acceptable to use simple Monte Carlo software on strictly rectangular geometries to generate ground rules. However, as the industry advances, designs have become more complex and design density has become a greater issue. As such, it is imperative that intersect area software tools progress to a higher level to address the complexities of advanced technologies.